	AREA constant_declaration, DATA, READONLY

PERIPH_BASE EQU 0x40000000 ;Peripheral base address in the alias region

; reset and clock
AHBPERIPH_BASE EQU (PERIPH_BASE + 0x20000)
RCC_BASE EQU (AHBPERIPH_BASE + 0x1000)

RCC_APB2ENR EQU (RCC_BASE +0x018) ; Address of APB2ENR to enable clock


RCC_APB2ENR_GPIOAEN_mask EQU (0x00000004) ; GPIO port A clock enable	
RCC_APB2ENR_GPIOBEN_mask EQU (0x00000008) ; GPIO port B clock enable
RCC_APB2ENR_GPIOCEN_mask EQU (0x00000010) ; GPIO port C clock enable	
RCC_APB2ENR_GPIODEN_mask EQU (0x00000020) ; GPIO port D clock enable		
	





;GPIO
APB2PERIPH_BASE EQU (PERIPH_BASE + 0x10000)

GPIOA_BASE EQU (APB2PERIPH_BASE + 0x0800)
GPIOB_BASE EQU (APB2PERIPH_BASE + 0x0C00)
GPIOC_BASE EQU (APB2PERIPH_BASE + 0x1000)
GPIOD_BASE EQU (APB2PERIPH_BASE + 0x1400)
GPIOE_BASE EQU (APB2PERIPH_BASE + 0x1800)
GPIOF_BASE EQU (APB2PERIPH_BASE + 0x1C00)
GPIOG_BASE EQU (APB2PERIPH_BASE + 0x2000)



GPIOx_CRL EQU 0x00
GPIOx_CRH EQU 0x04
GPIOx_IDR EQU 0x08
GPIOx_ODR EQU 0x0C



GPIOD_CRL EQU (GPIOD_BASE + GPIOx_CRL) ; PORTD control register low
GPIOD_ODR EQU (GPIOD_BASE + GPIOx_ODR) ; PORTD output data
GPIOD_IDR EQU (GPIOD_BASE + GPIOx_IDR) ; PORTD input data



	END
